Memory devices typically have several independently accessible arrays or ‘banks’ of memory cells for storing information. A bit of information is written to or read from a particular memory cell by selecting the bank and activating the row and column in the bank at the intersection of which is located the desired memory cell. Information is stored in the activated memory cell by either charging or discharging a capacitor included in the cell. Charge stored on memory cell capacitors leaks out over time, causing data loss if not addressed. To ensure proper data retention, information stored in leaky memory cells is periodically refreshed. Examples of memory devices that suffer from memory cell leakage include Dynamic Random Access Memory (DRAM) devices.
A DRAM device typically performs a refresh operation in response to a refresh command issued to the device. During the refresh operation, normal memory device operation is suspended and one or more rows (also referred to as word lines) of memory cells are refreshed. The refresh operation must be completed within a predetermined amount of time. For example, 256 Mb DDR2 (double-data rate, version 2) DRAM devices must perform a refresh operation in 75 ns or less. 512 Mb DDR2 DRAM devices are allocated 105 ns, 1 Gb DDR2 DRAM devices 127.5 ns, 2 Gb DDR2 DRAM devices 195 ns and 4 Gb DDR2 DRAM devices 327.5 ns.
Current spikes each time a row of memory cells is activated during a refresh operation. To alleviate problematic power supply excursions, even and odd banks are conventionally grouped separately and refreshed at different times. One or more rows of memory cells are refreshed in the even group of banks followed by the same row or rows being refreshed in the odd group of banks. This way, not all rows to be refreshed are activated at the same time. Instead, row activation is spread across even and odd bank groupings during a conventional refresh operation. Additional refresh commands are issued until all rows within the memory device are refreshed within a rolling time interval, e.g., 64 ms.
As memory devices continue to expand in size, so to does the number of word lines requiring periodic refreshing. Yet, the time allocated to perform a refresh operation usually does not scale correspondingly, e.g., as identified above for some types of DDR2 DRAM devices. Otherwise, device performance degrades when refresh operations consume excessive time. Thus, conventional DRAM devices simultaneously refresh multiple word lines per even bank followed by multiple word lines per odd bank to ensure refresh operations are completed within the allocated time. For example, a conventional 1 Gb DRAM device typically refreshes two word lines simultaneously in each even bank followed by two word lines in each odd bank. The number of word lines doubles when the device is scaled to a 2 Gb capacity. Yet, the refresh period allocated to the 2 Gb device does not scale correspondingly. As such, four word lines are conventionally refreshed for each group of banks instead of two word lines, exasperating the current spikes that occur during refresh operations compared to the previous generation. The problem worsens each time the device size increases, requiring more word lines to be simultaneously refreshed.